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-- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains
-- Project :
-- File    :
-- Autor   :
-- Date    :
--
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-- Description :
--
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library ieee;
  use ieee.std_logic_1164.all;
  --use ieee.numeric_std.all;

entity VHDL_Component is
  port(
  ------------------------------------------------------------------------------
  --Insert input ports below
    horloge_i  : in  std_logic;                    -- input bit example
    val_i      : in  std_logic_vector(3 downto 0); -- input vector example
  ------------------------------------------------------------------------------
  --Insert output ports below
    max_o      : out std_logic;                    -- output bit example
    cpt_o      : out std_logic_vector(3 downto 0)  -- output vector example
    );
end VHDL_Component;

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--Complete your VHDL description below
architecture type_architecture of VHDL_Component is


begin


end type_architecture;
